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xr16l2550 -industry smallest package uart with 2.25v to 5.5v operation home news careers investor relations contact us partnernet login search communications interface power management support info request how to order samples how to buy design technical documentation technical faqs product finder product tree technical support packaging evaluation boards cross references product change notifications obsolescence interface brochure ibis models bsdl ici uart finder xr16l2550 print this page industry smallest package uart with 2.25v to 5.5v operation features l small 32-qfn package of 5x5x0.9mm l wide range supply voltage operation of 2.25v to 5.5v l automatic rts/cts hardware flow control l automatic xon/xoff software flow control l 16-byte transmit/receive fifo to reduce bandwidth requirements of external cpu l wireless infrared encoder and decoder l full modem interface (txd, rxd, rts, cts, dtr, dsr, ri, cd) l pb-free, rohs compliant versions offered applications l handheld appliances l battery operated instruments l portable appliances l cdma cellular phones l cellular base stations l telecommunications network routers l industrial automation controls description this dual-channel product family is highly integrated and built for small board space, low voltage and high bandwidth requirements found in a variety of handheld and battery operated applications. these include point-of-sale (pos) terminals, tablets and notepads, cdma cellular phones, expansion modules, instrumentation, cellular base stations, wireless infrared appliances and industrial automation controls. the series consists of four devices: xr16l2450, xr16l2550, xr16l2551 and xr16l2552. each has two independently controlled uart channels and operates over a broad range power source of 2.25v to 5.5v with 5v tolerant inputs. the xr16l2551 uniquely offers a very small 32-qfn, 5x5x0.9mm, package with powersave feature to conserve power down to less than 30ua* of current consumption. these attributes are a perfect specifications ch 2 cpuinterface intel data rate@5/3.3/2.5v 3.1/1.8/1.0 tx/rxfifo(bytes) 16/16 tx/rxfifoctrs no tx/rxfifoint trig no/ 4 levels autorts/cts yes irdasup yes 5vtolinputs yes sup v 2.25-5.5 pkgs plcc-44, qfn-32, tqfp-48 documents datasheets datasheet version 1.1.2 may 2007 885.36 kb application notes dan-138, exar's xr16l2550 compared to ti's tl16c752b version 1.0.0 november 2003 69.59 kb http://www.exar.com/common/content/productdetails.aspx?id=xr16l2550 (1 of 2) [31-jul-09 9:36:38 am]
xr16l2550 -industry smallest package uart with 2.25v to 5.5v operation quality and reliability quality & reliability homepage material declaration sheets quality manual quarterly quality & reliability report rohs-green solutions combination for tight space and/or battery operated designs. the powersave feature eliminates the need for two external octal transceivers to reduce board space requirement and lower overall system costs. the xr16l2551 also offers a pin select for intel or motorola data bus interface to reduce hardware design cycle. the xr16l2550, xr16l2551 and xr16l2552 have 16-byte of tx and rx fifos for larger data buffering and provide automatic hardware (rts/cts) or software (xon/xoff) flow control to eliminate receiver data overflow and wasteful re-transmissions. in addition, the devices include the wireless infrared encoder/decoder for wireless communications. the xr16l2450 has one byte of tx and rx fifo as its predecessor, the st16c2450, but with lower operating voltage and 5v tolerant inputs. the 4 devices are pin and function compatible with their previous 5v series. for uart technical support or to obtain an ibis model for this product, please email exar's uart technical support group. part number pkg code rohs min temp. (c) max temp. (c) status buy now order samples xr16l2550ij-f plcc44 -40 85 active xr16l2550il qfn32 -40 85 active XR16L2550IL-F qfn32 -40 85 active xr16l2550im-f tqfp48 -40 85 active part status legend active - the part is released for sale, standard product. eol (end of life) - the part is no longer being manufactured, there may or may not be inventory still in stock. cf (contact factory) - the part is still active but customers should check with the factory for availability. longer lead-times may apply. pre (pre-introduction) - the part has not been introduced or the part number is an early version available for sample only. obs (obsolete) - the part is no longer being manufactured and may not be ordered. nrnd (not recommended for new designs) - the part is not recommended for new designs. schematics pci eval board schematic version 1.1.0 july 2007 167.82 kb isa eval board schematic version 1.4.0 august 2007 109.05 kb evaluation board manuals evaluation board user's manual version 1.3.0 august 2003 24.69 kb ? 2000-2009 exar corporation, fremont california, u.s.a. terms of use | site map http://www.exar.com/common/content/productdetails.aspx?id=xr16l2550 (2 of 2) [31-jul-09 9:36:38 am]
exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com xr16l2550 low voltage duart with 16-byte fifo may 2007 rev. 1.1.2 general description the xr16l2550 1 (l2550) is a dual universal asynchronous receiver and transmitter (uart). the xr16l2550 is an improved version of the st16c2550 uart with lower operating voltages and 5 volt tolerant inputs. the l2550 provides enhanced uart functions with 16 byte fifos, a modem control interface and data rates up to 4 mbps. onboard status registers provide the user with error indications and operational status. system interrupts and modem control features may be tailored by external software to meet specific user requirements. independent programmable baud rate generators are provided to select transmit and receive clock rates up to 3.125 mbps. the baud rate generator can be configured for either crystal or external clock input. an internal loopback capability allows onboard diagno stics. the l2550 is available in a 44-pin plcc, 48-pin tqfp and 32-pin qfn packages. the l2550 is fabricated in an advanced cmos process. n ote : 1 covered by u.s. patent #5,649,122. applications ? ? ? ? ? ? features ? ? ? ? ? ? ? ?
xr16l2550 2 low voltage duart with 16-byte fifo rev. 1.1.2 f igure 2. p in o ut a ssignment ordering information p art n umber p ackage o perating t emperature r ange d evice s tatus xr16l2550il 32-lead qfn -40c to +85c active xr16l2550ij 44-lead plcc -40c to +85c active xr16l2550im 48-lead tqfp -40c to +85c active 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 d5 d6 d7 rxb rxa txrdyb# txa txb op2b# csa# csb# nc xtal1 xtal2 iow# cdb# gnd rxrdyb# ior# dsrb# rib# rtsb# ctsb# nc reset dtrb# dtra# rtsa# op2a# rxrdya# inta intb a0 a1 a2 nc d4 d3 d2 d1 d0 txrdya# vcc ria# cda# dsra# ctsa# nc xr16l2550 48-pin tqfp 6 5 4 3 2 1 44 43 42 41 40 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 d5 d6 d7 rxb rxa txrdyb# txa txb op2b# csa# csb# reset dtrb# dtra# rtsa# op2a# rxrdya# inta intb a0 a1 a2 xtal1 xtal2 iow# cdb# gnd rxrdyb# ior# dsrb# rib# rtsb# ctsb# d4 d3 d2 d1 d0 txrdya# vcc ria# cda# dsra# ctsa# xr16l2550 44-pin plcc 32 31 30 29 1 2 3 4 5 6 7 8 24 23 22 21 20 19 11 12 13 14 15 16 9 10 d5 d6 d7 rxb rxa txa txb csa# csb# xtal1 xtal2 iow# gnd ior # rtsb# ctsb# reset rtsa# inta intb a0 a1 a2 d4 d3 d2 d1 d0 vcc ctsa# xr16l2550 32-pin qfn 28 27 26 25 18 17 nc nc
xr16l2550 3 rev. 1.1.2 low voltage duart with 16-byte fifo pin descriptions pin description n ame 32-qfn p in # 44-plcc p in # 48-tqfp p in # t ype d escription data bus interface a2 a1 a0 18 19 20 29 30 31 26 27 28 i address data lines [2:0]. these 3 address lines select one of the internal registers in uart channel a/b during a data bus transac - tion. d7 d6 d5 d4 d3 d2 d1 d0 2 1 32 31 30 29 28 27 9 8 7 6 5 4 3 2 3 2 1 48 47 46 45 44 io data bus lines [7:0 ] (bidirectional). ior# 14 24 19 i input/output read strobe (active low). the falling edge instigates an internal read cycle and retrieves the data byte from an internal register pointed to by the address lines [a2:a0]. the data byte is placed on the data bus to allow the host processor to read it on the rising edge. iow# 12 20 15 i input/output write strobe (activ e low). the falling edge instigates an internal write cycle and the rising edge transfers the data byte on the data bus to an internal register pointed by the address lines. csa# 7 16 10 i uart channel a select (active low) to enable uart channel a in the device for data bus operation. csb# 8 17 11 i uart channel b select (active low) to enable uart channel b in the device for data bus operation. inta 22 33 30 o uart channel a interrupt output . the output state is defined by the user and through the software setting of mcr[3]. inta is set to the active mode (active high) and op2a# output to a logic 0 when mcr[3] is set to a logic 1. inta is set to the three state mode and op2a# to a logic 1 when mcr[3] is set to a logic 0 (default). intb 21 32 29 o uart channel b interrupt output . the output state is defined by the user and through the software setting of mcr[3]. intb is set to the active mode and op2b# output to a logic 0 when mcr[3] is set to a logic 1. intb is set to the three state mode and op2b# to a logic 1 when mcr[3] is set to a logic 0 (default). txrdya# - 1 43 o uart channel a transmitter re ady (active low). the output provides the tx fifo/thr status for transmit channel a. if it is not used, leave it unconnected. rxrdya# - 34 31 o uart channel a receiver ready (active low). this output pro - vides the rx fifo/rhr status for receive channel a. if it is not used, leave it unconnected.
xr16l2550 4 low voltage duart with 16-byte fifo rev. 1.1.2 txrdyb# - 12 6 o uart channel b transmitter ready (active low). the output pro - vides the tx fifo/thr status for transmit channel b. if it is not used, leave it unconnected. rxrdyb# - 23 18 o uart channel b receiver ready (active low). this output pro - vides the rx fifo/rhr status for receive channel b. if it is not used, leave it unconnected. modem or serial i/o interface txa 5 13 7 o uart channel a transmit data. if it is not used, leave it uncon - nected. rxa 4 11 5 i uart channel a receive data. normal receive data input must idle at logic 1 condition. if it is no t used, tie it to vcc or pull it high via a 100k ohm resistor. rtsa# 23 36 33 o uart channel a request-to-send (active low) or general pur - pose output. this output must be asserted prior to using auto rts flow control, see efr[6], mcr[1] and ier[6]. if it is not used, leave it unconnected. ctsa# 25 40 38 i uart channel a clear-to-send (active low) or general purpose input. it can be used for auto cts flow control, see efr[7] and ier[7]. this input should be connected to vcc when not used. dtra# - 37 34 o uart channel a data-terminal-ready (active low) or general purpose output. if it is no t used, leave it unconnected. dsra# - 41 39 i uart channel a data-set-ready (active low) or general purpose input. this input should be connected to vcc when not used. this input has no effect on the uart. cda# - 42 40 i uart channel a carrier-detect (a ctive low) or general purpose input. this input should be connected to vcc when not used. this input has no effect on the uart. ria# - 43 41 i uart channel a ring-indicator (active low) or general purpose input. this input should be connected to vcc when not used. this input has no effect on the uart. op2a# - 35 32 o output port 2 channel a - the output state is defined by the user and through the software setting of mcr[3]. inta is set to the active mode and op2a# output to a logic 0 when mcr[3] is set to a logic 1. inta is set to the three state mode and op2a# to a logic 1 when mcr[3] is set to a logic 0. this output should not be used as a general output else it will disturb the inta output func - tionality. if it is not used at all, leave it unconnected. txb 6 14 8 o uart channel b transmit data. if it is not used, leave it uncon - nected. rxb 3 10 4 i uart channel b receive data. normal receive data input must idle at logic 1 condition. if it is no t used, tie it to vcc or pull it high via a 100k ohm resistor. pin description n ame 32-qfn p in # 44-plcc p in # 48-tqfp p in # t ype d escription
xr16l2550 5 rev. 1.1.2 low voltage duart with 16-byte fifo pin type: i=input, o=output, io= i nput/output, od=output open drain. rtsb# 15 27 22 o uart channel b request-to-send (active low) or general pur - pose output. this output must be asserted prior to using auto rts flow control, see efr[6], mcr[1] and ier[6]. if it is not used, leave it unconnected. ctsb# 16 28 23 i uart channel b clear-to-send (active low) or general purpose input. it can be used for auto cts flow control, see efr[7] and ier[7]. this input should be connected to vcc when not used. dtrb# - 38 35 o uart channel b data-terminal-ready (active low) or general purpose output. if it is no t used, leave it unconnected. dsrb# - 25 20 i uart channel b data-set-ready (active low) or general purpose input. this input should be connected to vcc when not used. this input has no effect on the uart. cdb# - 21 16 i uart channel b carrier-detect (a ctive low) or general purpose input. this input should be connected to vcc when not used. this input has no effect on the uart. rib# - 26 21 i uart channel b ring-indicator (active low) or general purpose input. this input should be connected to vcc when not used. this input has no effect on the uart. op2b# - 15 9 o output port 2 channel b - the output state is defined by the user and through the software setting of mcr[3]. intb is set to the active mode and op2b# output to a logic 0 when mcr[3] is set to a logic 1. intb is set to the three state mode and op2b# to a logic 1 when mcr[3] is set to a logic 0. this output should not be used as a general output else it will disturb the intb output func - tionality. if it is not used, leave it unconnected. ancillary signals xtal1 10 18 13 i crystal or external clock input. xtal2 11 19 14 o crystal or buffered clock output. reset 24 39 36 i reset (active high) - a longer than 40 ns logic 1 pulse on this pin will reset the internal registers and all outputs. the uart trans - mitter output will be held at logic 1, the receiver input will be ignored and outputs are reset during reset period. vcc 26 44 42 pwr 2.25v to 5.5v power supply. all inputs are 5v tolerant. gnd 13 22 17 pwr power supply common, ground. gnd center pad n/a n/a pwr the center pad on the backside of the 32-qfn package is metal - lic and should be connected to gnd on the pcb. the thermal pad size on the pcb should be the approximate size of this cen - ter pad and should be solder mask defined. the solder mask opening should be at least 0.0025" inwards from the edge of the pcb thermal pad. n.c. 9, 17 - 12, 24, 25, 37 no connection. these pins are open, but typically, should be con - nected to gnd for good design practice. pin description n ame 32-qfn p in # 44-plcc p in # 48-tqfp p in # t ype d escription
xr16l2550 6 low voltage duart with 16-byte fifo rev. 1.1.2 1.0 product description the xr16l2550 (l2550) provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-parallel data conversions for both the tran smitter and receiver sections. these functions are necessary for converting the serial data stream into para llel data that is required with digital data systems. synchronization for the serial data stream is accomplished by adding start and stop bits to the transmit data to form a data character (character orientated protocol). da ta integrity is ensured by at taching a parity bit to the data character. the parity bit is checked by the receiv er for any transmission bit errors. the electronic circuitry to provide all these functions is fair ly complex especially when manufactur ed on a single in tegrated silicon chip. the l2550 represents such an integration with gr eatly enhanced features. the l2550 is fabricated with an advanced cmos process. transmit and receive fifos (16 bytes each) the l2550 is an upward solution th at provides a dual uart capability wi th 16 bytes of tran smit and receive fifo memory, instead of none in the 16c2450. the l2550 is designed to work with high speed modems and shared network environments, that require fast data proc essing time. increased performance is realized in the l2550 by the transmit and receive fifo?s. this allows the external processor to handle more networking tasks within a given time. for example, the st16c2450 without a receive fifo, w ill require unloading of the rhr in 93 microseconds (this example uses a character length of 11 bits, including start/stop bits at 115.2 kbps). this means the external cpu will have to service the rece ive fifo less than every 10 0 microseconds. however with the 16 byte fifo in the l2550, the data buffer will not require unlo ading/loading for 1.53 ms. this increases the service interval giving the external cpu add itional time for other applications and reducing the overall uart interrupt servicing time. in addition, the 4 selectable receive fifo tr igger interrupt levels is uniquely provided for maximum data throughput perf ormance especially when operating in a multi-channel environment. the fifo memo ry greatly reduces the band width requirement of the external controlling cpu, increases performance, and reduces power consumption. data rate the l2550 is capable of operation up to 3.125 mbps with a 50 mhz clock. with a crystal or external clock input of 14.7456 mhz the user can select data rates up to 921.6 kbps. enhanced features the xr16l2550 integrates the func tions of 2 enhanced 16c550 universal asynchronous receiver and transmitter (uart). each uart is independently cont rolled having its own set of device configuration registers. the configuration registers set is 16550 ua rt compatible for control, status and data transfer. additionally, each uart channel has automatic rts/cts hardware flow control, automatic xon/xoff and special character software flow control, infrared enco der and decoder (irda ver 1.0), programmable baud rate generator with a prescaler of divide by 1 or 4, and data rate up to 4 mbps at 5v. the rich feature set of the l2550 is available through in ternal registers. selectable receive fifo trigger levels, selectable tx and rx baud rates, and modem interface controls are all standard features. following a power on reset or an external reset, the l2550 is functionally and software compatible with the previous generation st16c2450 and st16c2550.
xr16l2550 7 rev. 1.1.2 low voltage duart with 16-byte fifo 2.0 functional descriptions 2.1 cpu interface the cpu interface is 8 data bits wide with 3 address li nes and control signals to execute data bus read and write transactions. the l2550 data interface supports the inte l compatible types of cpus and it is compatible to the industry standard 16c550 uart. no clock (oscillator nor external clock) is requir ed to operate a data bus transaction. each bus cycle is asynchronous using cs#, ior# and iow# signals. both uart channels share the same data bus for host operations. t he data bus interconnections are shown in figure 3 . . 2.2 5-volt tolerant inputs the l2550 can accept up to 5v inputs even when oper ating at 3.3v or 2.5v. but note that if the l2550 is operating at 2.5v, its v oh may not be high enough to meet the requirements of the v ih of a cpu or a serial transceiver that is operating at 5v. 2.3 device reset the reset input resets the internal registers and the seri al interface outputs in both channels to their default state (see ta b l e 13 ). an active high pulse of at least 40 ns duration will be required to acti vate the reset function in the device. 2.4 device identification and revision the l2550 provides a device identification code and a devi ce revision code to distinguish the part from other devices and revisions. to read the identification code from the part, it is required to set the baud rate generator registers dll and dlm both to 0x00. now reading the content of th e dlm will provide 0x02 to indicate l2550 and reading the content of dll will pr ovide the revision of the part; for example, a reading of 0x01 means revision a. 2.5 channel a and b selection the uart provides the user with the capability to bi-directionally tr ansfer information be tween an external cpu and an external serial communication device. a lo gic 0 on chip select pins, csa# or csb#, allows the user to select uart channel a or b to configure, send transmit data and/or unload receive data to/from the uart. selecting both uarts can be useful during power up initialization to write to t he same internal registers, f igure 3. xr16l2550 d ata b us i nterconnections vcc vcc op2a# dsra# ctsa# rtsa# dtra# rxa txa ria# cda# op2b# dsrb# ctsb# rtsb# dtrb# rxb txb rib# cdb# gnd a0 a1 a2 uart_csa# uart_csb# ior# iow# d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 a2 csa# csb# d0 d1 d2 d3 d4 d5 d6 d7 ior# iow# uart channel a uart channel b uart_intb uart_inta intb inta rxrdya# txrdya# rxrdya# txrdya# rxrdyb# txrdyb# rxrdyb# txrdyb# uart_reset reset rs-232 serial interface rs-232 serial interface
xr16l2550 8 low voltage duart with 16-byte fifo rev. 1.1.2 but do not attempt to read from both uarts simultaneous ly. individual channel select functions are shown in table 1 . 2.6 channel a and b internal registers each uart channel in the l2 550 has a standard register set for cont rolling, monitoring an d data loading and unloading. the configuration register set is compatib le to those already available in the standard single 16c550. these registers function as data holding registers (thr/rhr), interrupt status and control registers (isr/ier), a fifo control register (fcr), receive line status and contro l registers (lsr/lcr), modem status and control registers (msr/mcr), programmable data rate (clock) divisor register s (dll/dlm), and a user accessible scratch pad register (spr). 2.7 dma mode the device does not support direct me mory access. the dma mode (a legacy term) in this document doesn?t mean ?direct memory access? but refers to data block transfer operation. the dma mode affects the state of the rxrdy# a/b and txrdy# a/b output pins. the transmit and receive fifo trigger levels provide additional flexibility to the user for block mode operation. the lsr bits 5- 6 provide an indication when the transmitter is empty or has an empty location(s) for more data. the user can optionally operate the transmit and receive fifo in the dma mode (fcr bit-3=1). when the transmit and receive fifo are enabled and the dma mode is disabled (fcr bit-3 = 0), the l2550 is placed in sing le-character mode for data transmit or receive operation. when dma mode is enabled (fcr bit-3 = 1), the user takes advantage of block mode operation by loading or unloading the fifo in a block sequence determined by the programmed trigger level. the following table show their behavior. also see figure 18 through figure 23 . 2.8 inta and intb outputs the inta and intb interrupt output changes according to the operating mode and enhanced features setup. table 3 and table 4 summarize the operating behavior for the transmitter and receiver. also see figure 18 through figure 23 . t able 1: c hannel a and b s elect csa# csb# f unction 1 1 uart de-selected 0 1 channel a selected 1 0 channel b selected 0 0 channel a and b selected t able 2: txrdy# and rxrdy# o utputs in fifo and dma m ode p ins fcr bit -0=0 (fifo d isabled ) fcr b it -0=1 (fifo e nabled ) fcr bit-3 = 0 (dma mode disabled) fcr bit-3 = 1 (dma mode enabled) rxrdy# a/b 0 = 1 byte. 1 = no data. 0 = at least 1 byte in fifo 1 = fifo empty. 1 to 0 transition when fifo reaches the trigger level, or time-out occurs. 0 to 1 transition when fifo empties. txrdy# a/b 0 = thr empty. 1 = byte in thr. 0 = fifo empty. 1 = at least 1 byte in fifo. 0 = fifo has at least 1 empty location. 1 = fifo is full.
xr16l2550 9 rev. 1.1.2 low voltage duart with 16-byte fifo 2.9 crystal oscillator or external clock input the l2550 includes an on-chip oscillator (xtal1 and xtal2) to produce a clock for both uart sections in the device. the cpu data bus does not r equire this clock for bus operation. the crystal oscillator provides a system clock to the baud rate generators (brg) section found in each of the uart. xtal1 is the input to the oscillator or external clock buffer input with xtal 2 pin being the output. fo r programming details, see ?programmable baud rate generator.? the on-chip oscillator is designed to use an industry stand ard microprocessor cryst al (parallel resonant, fundamental frequency with 10-22 pf capacitance load, esr of 20-120 ohms and 100 ppm frequency tolerance) connected externally betw een the xtal1 and xtal2 pins (see figure 4 ), with an external 500 k ? ? ? 500 ? ? 1 ?
xr16l2550 10 low voltage duart with 16-byte fifo rev. 1.1.2 2.10 programmable baud rate generator a single baud rate generator is provided for the trans mitter and receiver, allowing independent tx/rx channel control. the programmable baud rate generator is capa ble of operating with a crystal frequency of up to 24 mhz. however, with an external clock input on xtal 1 pin and a 2k ohms pull-up resistor on xtal2 pin (as shown in figure 5 ) it can extend its operation up to 64 mhz (4mbps serial data rate) at room temperature and 5.0v. to obtain maximum data rate, it is necessary to use full rail swing on the clock input. see external clock operating frequency over power supply voltage chart in figure 6 . f igure 5. e xternal c lock c onnection for e xtended d ata r ate f igure 6. o perating f requency c hart . r equires a 2k ohms pull - up resistor on xtal2 pin to increase operating speed 2k xtal1 xtal2 r1 vcc external clock vcc gnd 60 50 40 30 3.0 4.5 5.5 3.5 4.0 5.0 suppy voltage xtal1 external clock frequency in mhz. 70 80 85 o c 25 o c -40 o c operating frequency for xr16l2550 with external clock and a 2k ohms pull-up resistor on xtal2 pin.
xr16l2550 11 rev. 1.1.2 low voltage duart with 16-byte fifo the l2550 divides the basic external clock by 16. the basic 16x clock provides table rates to support standard and custom applications using the same system design. the baud rate generator divides the input 16x clock by any divisor from 1 to 2 16 -1. the rate table is configured via t he dll and dlm internal register functions. customized baud rates can be achieved by selecting th e proper divisor values for the msb and lsb sections of baud rate generator. table 5 shows the standard data rates available with a 14.7456 mhz crystal or external clock at 16x sampling rate. when using a non-standard frequency crystal or ex ternal clock, the divisor value can be calculated for dll/dlm with the following equation. 2.11 transmitter the transmitter section comprises of an 8-bit transmit shift register (tsr) and 16 bytes of fifo which includes a byte-wide transmit holding register (thr). tsr shifts out every data bit with the 16x internal clock. a bit time is 16 clock periods. the transmitter sends the start-bit followed by the number of data bits, inserts the proper parity-bit if enabled, and adds the stop -bit(s). the status of the fifo and tsr are reported in the line status register (lsr bit-5 and bit-6). 2.11.1 transmit holding re gister (thr) - write only the transmit holding register is an 8-bit register pr oviding a data interface to the host processor. the host writes transmit data byte to the thr to be converted in to a serial data stream including start-bit, data bits, parity-bit and stop-bit(s). the least-si gnificant-bit (bit-0) becomes first data bit to go out. the thr is the input register to the transmit fifo of 16 bytes when fifo operation is enabl ed by fcr bit-0. every time a write operation is made to the thr, the fifo data pointer is automatically bumped to the next sequential data location. 2.11.2 transmitter operation in non-fifo mode the host loads transmit data to thr one character at a time. the thr empty flag (lsr bit-5) is set when the data byte is transferred to tsr. thr flag can generate a transmit empty interrupt (isr bit-1) when it is enabled by ier bit-1. the tsr flag (lsr bit-6) is set when tsr beco mes completely empty. divisor (decimal) = (xtal1 clock frequency) / (serial data rate x 16) t able 5: t ypical data rates with a 14.7456 mh z crystal or external clock o utput data rate mcr bit-7=0 d ivisor for 16x clock (decimal) d ivisor for 16x clock (hex) dlm p rogram v alue (hex) dll p rogram v alue (hex) d ata r ate e rror (%) 400 2304 900 09 00 0 2400 384 180 01 80 0 4800 192 c0 00 c0 0 9600 96 60 00 60 0 19.2k 48 30 00 30 0 38.4k 24 18 00 18 0 76.8k 12 0c 00 0c 0 153.6k 6 06 00 06 0 230.4k 4 04 00 04 0 460.8k 2 02 00 02 0 921.6k 1 01 00 01 0
xr16l2550 12 low voltage duart with 16-byte fifo rev. 1.1.2 2.11.3 transmitter operation in fifo mode the host may fill the transmit fifo with up to 16 bytes of transmit data. t he thr empty flag (lsr bit-5) is set whenever the fifo is empty. the thr empty flag can ge nerate a transmit empty interrupt (isr bit-1) when the transmit empty interrupt is enabled by ier bit-1. the tsr flag (lsr bit-6) is set when the fifo and the tsr become empty. 2.12 receiver the receiver section contains an 8-bit receive shift register (rsr) and 16 bytes of fifo which includes a byte-wide receive holding regi ster (rhr). the rsr uses the 16x for ti ming. it verifies and validates every bit on the incoming character in the middle of each data bit. on the falling edge of a start or false start bit, an internal receiver counter star ts counting at the 16x. after 8 clocks the start bit period should be at the center of the start bit. at this time the start bit is sampled and if it is still a logic 0 it is validated. evaluati ng the start bit in this manner prevents the receiver from assembling a false ch aracter. the rest of the data bits and stop bits are sampled and validated in this same manner to prevent false framing. if there were any error(s), they are reported in the lsr register bits 2-4. upon unloading th e receive data byte from rhr, the receive fifo pointer is bumped and the error tags are immediately updated to reflect the status of the data byte in rhr register. rhr can generate a receive data ready interrupt upon rece iving a character or delay until it reaches the fifo trigger level. furthermore, data delivery to the host is guaranteed by a receive data ready time-out interrupt f igure 7. t ransmitter o peration in non -fifo m ode f igure 8. t ransmitter o peration in fifo and f low c ontrol m ode transmit holding register (thr) transmit shift register (tsr) data byte l s b m s b thr interrupt (isr bit-1) enabled by ier bit-1 txnofifo1 16x clock transmit data shift register (tsr) transmit data byte thr interrupt (isr bit-1) falls below the programmed trigger level and then when becomes empty. fifo is enabled by fcr bit-0=1 transmit fifo 16x clock auto cts flow control (cts# pin) auto software flow control flow control characters (xoff1/2 and xon1/2 reg. txfifo1
xr16l2550 13 rev. 1.1.2 low voltage duart with 16-byte fifo when data is not received for 4 word lengths as defined by lcr[1:0] plus 12 bits ti me. this is equivalent to 3.7- 4.6 character times. the rhr interrupt is enabled by ier bit-0. 2.12.1 receive holding register (rhr) - read-only the receive holding register is an 8-bit register that holds a receive data byte from the receive shift register. it provides the receive data interface to the host processor. the rhr register is part of the receive fifo of 16 bytes by 11-bits wide, the 3 extra bits are fo r the 3 error tags to be reported in lsr register. when the fifo is enabled by fcr bit-0, the rhr contains th e first data character received by the fifo. after the rhr is read, the next character byte is loaded into the rhr and the errors associated with the current data byte are immediately updated in the lsr bits 2-4. f igure 9. r eceiver o peration in non -fifo m ode f igure 10. r eceiver o peration in fifo and a uto rts f low c ontrol m ode receive data shift register (rsr) receive data byte and errors rhr interrupt (isr bit-2) receive data holding register (rhr) rxfifo1 16x clock receive data characters data bit validation error tags in lsr bits 4:2 receive data shift register (rsr) rxfifo1 16x clock error tags (16-sets) error tags in lsr bits 4:2 16 bytes by 11-bit wide fifo receive data characters fifo trigger=8 example : - rx fifo trigger level selected at 8 bytes data fills to 14 data falls to 4 data bit validation receive data fifo receive data receive data byte and errors rhr interrupt (isr bit-2) programmed for desired fifo trigger level. fifo is enabled by fcr bit-0=1 rts# de-asserts when data fills above the flow control trigger level to suspend remote transmitter. enable by efr bit-6=1, mcr bit-2. rts# re-asserts when data falls below the flow control trigger level to restart remote transmitter. enable by efr bit-6=1, mcr bit-2.
xr16l2550 14 low voltage duart with 16-byte fifo rev. 1.1.2 2.13 auto rts (hardware) flow control automatic rts hardware flow control is used to prevent data overrun to the local receiver fifo. the rts# output is used to request remote unit to suspend/r esume data transmission. the auto rts flow control features is enabled to fit specific application requirement (see figure 11 ): ? ? ? 2.14 auto cts flow control automatic cts flow control is used to prevent data overrun to the remote receiver fifo. the cts# input is monitored to suspend/restart the local transmitter. the aut o cts flow control feature is selected to fit specific application requirement (see figure 11 ): ? ?
xr16l2550 15 rev. 1.1.2 low voltage duart with 16-byte fifo f igure 11. a uto rts and cts f low c ontrol o peration the local uart (uarta) starts data transfer by asserting rtsa# (1). rtsa# is normally connected to ctsb# (2) of remote uart (uartb). ctsb# allows its transmitter to se nd data (3). txb data arrives and fills uarta receive fifo (4). when rxa data fills up to its receive fifo trigger le vel, uarta activates its rxa data ready interrupt (5) and con - tinues to receive and put data into its fifo. if interrupt se rvice latency is long and data is not being unloaded, uarta monitors its receive data fill level to match the upper thre shold of rts delay and de-assert rtsa# (6). ctsb# follows (7) and request uartb transmitter to suspend data transfer. ua rtb stops or finishes sending the data bits in its trans - mit shift register (8). when receive fifo data in uarta is unloaded to match the lower threshold of rts delay (9), uarta re-asserts rtsa# (10), ctsb# recognizes the change (11) and restarts its transmitter and data flow again until next receive fifo trigger (12). this same event applies to the reverse direction when uarta sends data to uartb with rtsb# and ctsa# controlling the data flow. rtsa# ctsb# rxa txb transmitter receiver fifo trigger reached auto rts trigger level auto cts monitor rtsa# txb rxa fifo ctsb# remote uart uartb local uart uarta on off on suspend restart rts high threshold data starts on off on assert rts# to begin transmission 1 2 3 4 5 6 7 receive data rts low threshold 9 10 11 receiver fifo trigger reached auto rts trigger level transmitter auto cts monitor rtsb# ctsa# rxb txa inta (rxa fifo interrupt) rx fifo trigger level rx fifo trigger level 8 12 rtscts1
xr16l2550 16 low voltage duart with 16-byte fifo rev. 1.1.2 2.15 auto xon/xoff (software) flow control when software flow control is enabled ( see table 12 ), the l2550 compares one or two sequential receive data characters with the programmed xon or xoff-1,2 charac ter value(s). if receive character(s) (rx) match the programmed values, the l2550 will halt transmission (tx) as soon as the current c haracter has completed transmission. when a match occurs, the xoff (if enabled vi a ier bit-5) flag will be set and the interrupt output pin will be activated. following a susp ension due to a match of the xoff character, the l 2550 will monitor the receive data stream fo r a match to the xon-1,2 character. if a matc h is found, the l2550 will resume operation and clear the flags (isr bit-4). reset initially sets the contents of the xon/xoff 8-bit flow control registers to a logic 0. following reset the user can write any xon/xoff value desired for software flow c ontrol. different conditions can be set to detect xon/ xoff characters ( see table 12 ) and suspend/resume transmissions. when double 8-bit xon/xoff characters are selected, the l2550 compares tw o consecutive receive characters wit h two software flow control 8-bit values (xon1, xon2, xoff1, xoff2) and controls tx tran smissions accordingly. under the above described flow control mechanisms, flow control charac ters are not placed (stacked) in the user accessible rx data buffer or fifo. in the event that the receive buffer is overfilling and flow control needs to be executed, the l2550 automatically sends an xoff message (when enabled) via the serial tx output to the remote modem. the l2550 sends the xoff-1,2 characters two-character-times (= time taken to send two characters at the programmed baud rate) after the receive fifo crosses the prog rammed trigger level. to clear this condition, th e l2550 will transmit the programmed xon-1,2 characters as soon as receive fifo is less than one trigge r level below the programmed trigger level. see table 6 below. * after the trigger level is reached, an xoff character is se nt after a short span of time (= time required to send 2 characters); for example, after 2.083ms has elapsed for 9600 b aud and 8-bit word length, no parity and 1 stop bit setting. 2.16 special character detect a special character detect feature is provided to detect an 8-bit character when bit-5 is set in the enhanced feature register (efr). when this character (xoff2) is detected, it will be placed in the fi fo along with normal incoming rx data. the l2550 compares each incoming receive characte r with xoff-2 data. if a matc h exists, the received data will be transferred to fifo and is r bit-4 will be set to indicate detection of special character. al though the internal register table shows xon, xoff registers with eight bits of character information, the actual number of bits is dependent on the programmed word lengt h. line control register (lcr) bits 0-1 defines the number of character bits, i.e., either 5 bits, 6 bits, 7 bits, or 8 bits. the word length selected by lcr bits 0-1 also determines the number of bits that will be used for the special character comparison. bit-0 in the xon, xoff registers corresponds with the ls b bit for the receive character. t able 6: a uto x on /x off (s oftware ) f low c ontrol rx t rigger l evel int p in a ctivation x off c haracter ( s ) s ent ( characters in rx fifo ) x on c haracter ( s ) s ent ( characters in rx fifo ) 1 1 1* 0 4 4 4* 1 8 8 8* 4 14 14 14* 8
xr16l2550 17 rev. 1.1.2 low voltage duart with 16-byte fifo 2.17 infrared mode the l2550 uart includes the infrared encoder and decoder compatible to the irda (infrared data association) version 1.0. the irda 1.0 standard th at stipulates the infrared encoder sends out a 3/16 of a bit wide high-pulse for each ?0? bit in the transmit data st ream. this signal encoding reduces the on-time of the infrared led, hence reduces the power consumption. see figure 12 below. the infrared encoder and decoder are enabled by setting mcr register bit-6 to a ?1?. when the infrared feature is enabled, the transmit data output, tx, idles at logic zero level. likewise, the rx input assumes an idle level of logic zero from a reset and power up, see figure 12 . typically, the wireless infrared decoder receives the input pulse from the infrared sensing diode on the rx pin. each time it senses a light pulse, it re turns a logic 1 to the data bit stream. f igure 12. i nfrared t ransmit d ata e ncoding and r eceive d ata d ecoding character data bits start stop 0000 0 11 111 bit time 1/16 clock delay irdecoder - rx data receive ir pulse (rx pin) character data bits start stop 0000 0 11 111 tx data transmit ir pulse (tx pin) bit time 1/2 bit time 3/16 bit time irencoder-1
xr16l2550 18 low voltage duart with 16-byte fifo rev. 1.1.2 2.18 sleep mode with auto wake-up the l2550 supports low voltage system designs, hence, a sleep mode is included to reduce its power consumption when the chip is not actively used. all of these conditions must be satisf ied for the l2550 to enter sleep mode:
xr16l2550 19 rev. 1.1.2 low voltage duart with 16-byte fifo 2.19 internal loopback the l2550 uart provides an intern al loopback capability for system diagnostic purposes. the internal loopback mode is enabled by setting mcr register bit-4 to logi c 1. all regular uart functions operate normally. figure 13 shows how the modem port signals are re-configured. transmit data from the transmit shift register output is internally routed to the receive shift register input allowing the system to re ceive the same data that it was sending. the tx pin is held at logic 1 or mark condition while rts# and dtr# are de-asserted, and cts#, dsr# cd# and ri# inputs are ignored. caution: th e rx input pins must be held to a logic 1 during loopback test else upon exiting the loopback test the ua rt may detect and report a false ?break? signal. also, auto rts/cts is not supported during internal loopback. f igure 13. i nternal l oop b ack in c hannel a and b txa/txb rxa/rxb modem / general purpose control logic internal data bus lines and control signals rtsa#/rtsb# mcr bit-4=1 vcc vcc transmit shift register (thr/fifo) receive shift register (rhr/fifo) ctsa#/ctsb# dtra#/dtrb# dsra#/dsrb# ria#/rib# cda#/cdb# op1# op2# rts# cts# dtr# dsr# ri# cd# vcc vcc op2a#/op2b#
xr16l2550 20 low voltage duart with 16-byte fifo rev. 1.1.2 3.0 uart internal registers each of the uart channel in the l2550 has its own set of configuration registers selected by address lines a0, a1 and a2 with csa# or csb# selecting the channel. the registers are 16c550 compatible. the complete register set is shown on table 7 and table 8 . t able 7: uart channel a and b uart internal registers a2,a1,a0 a ddresses r egister r ead /w rite c omments 16c550 c ompatible r egisters 0 0 0 rhr - receive holding register thr - transmit holding register read-only write-only lcr[7] = 0 0 0 0 dll - div latch low byte read/write lcr[7] = 1, lcr
xr16l2550 21 rev. 1.1.2 low voltage duart with 16-byte fifo t able 8: internal registers description. s haded bits are enabled when efr b it -4=1 a ddress a2-a0 r eg n ame r ead / w rite b it -7 b it -6 b it -5 b it -4 b it -3 b it -2 b it -1 b it -0 c omment 16c550 compatible registers 0 0 0 rhr rd bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7] = 0 0 0 0 thr wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 1 ier rd/wr 0/ 0/ 0/ 0/ modem stat. int. enable rx line stat. int. enable tx empty int enable rx data int. enable cts int. enable rts int. enable xoff int. enable sleep mode enable 0 1 0 isr rd fifos enabled fifos enabled 0/ 0/ int source bit-3 int source bit-2 int source bit-1 int source bit-0 lcr
xr16l2550 22 low voltage duart with 16-byte fifo rev. 1.1.2 4.0 internal register descriptions 4.1 receive holding register (rhr) - read- only see?receiver? on page 12. 4.2 transmit holding register (thr) - write-only see?transmitter? on page 11. 4.3 interrupt enable register (ier) - read/write the interrupt enable register (ier) masks the interrupts from receive data ready, transmit empty, line status and modem status registers. these interrupts are r eported in the interrupt status register (isr). 4.3.1 ier versus receive fifo interrupt mode operation when the receive fifo (fcr bit-0 = 1) and receive inte rrupts (ier bit-0 = 1) are enabled, the rhr interrupts (see isr bits 2 and 3) status will reflect the following: a. the receive data available interrupts are issued to the host when the fifo has reached the programmed trigger level. it will be cleared when the fifo drops below the programmed trigger level. b. fifo level will be reflected in the isr register when the fifo trigger level is reac hed. both the isr register status bit and the interrupt will be cleared wh en the fifo drops below the trigger level. c. the receive data ready bit (lsr bit-0) is set as soon as a character is transferred from the shift register to the receive fifo. it is rese t when the fifo is empty. 4.3.2 ier versus receive/transmit fifo polled mode operation when fcr bit-0 equals a logic 1 for fifo enable; rese tting ier bits 0-3 enables the xr16l2550 in the fifo polled mode of operation. since the receiver and transmitter have separate bits in the lsr either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). a. lsr bit-0 indicates there is data in rhr or rx fifo. b. lsr bit-1 indicates an overrun error has occurred and that data in the fifo may not be valid. c. lsr bit 2-4 provides the type of receive data erro rs encountered for the data byte in rhr, if any. d. lsr bit-5 indicates transmit fifo is empty. e. lsr bit-6 indicates when both the transmit fifo and tsr are empty. f. lsr bit-7 indicates a data error in at least one character in the rx fifo. enhanced registers 0 1 0 efr rd/wr auto cts enable auto rts enable special char select enable ier [7:4], isr [5:4], fcr[5:4], mcr[7:5] soft - ware flow cntl bit-3 soft - ware flow cntl bit-2 soft - ware flow cntl bit-1 soft - ware flow cntl bit-0 lcr=0 x bf 1 0 0 xon1 rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 0 1 xon2 rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 1 0 xoff1 rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 1 1 xoff2 rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 t able 8: internal registers description. s haded bits are enabled when efr b it -4=1 a ddress a2-a0 r eg n ame r ead / w rite b it -7 b it -6 b it -5 b it -4 b it -3 b it -2 b it -1 b it -0 c omment
xr16l2550 23 rev. 1.1.2 low voltage duart with 16-byte fifo ier[0]: rhr interrupt enable the receive data ready interrupt will be issued when rhr has a data characte r in the non-fifo mode or when the receive fifo has reached the programmed trigger level in the fifo mode. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 4.4 interrupt status register (isr) - read-only the uart provides multiple levels of prioritized interrupts to minimize external software interaction. the interrupt status register (isr) provides the user with six interrupt status bits. performing a read cycle on the isr will give the user the current hi ghest pending interrupt level to be se rviced, others are queued up to be serviced next. no other interrupts are acknowledged until the pending interrupt is serviced. the interrupt
xr16l2550 24 low voltage duart with 16-byte fifo rev. 1.1.2 source table, table 9 , shows the data values (bit 0-5) for the interrupt priority levels and the interrupt sources associated with each of these interrupt levels. 4.4.1 interrupt generation: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
xr16l2550 25 rev. 1.1.2 low voltage duart with 16-byte fifo isr[0]: interrupt status ? ? 4.5 fifo control register (fcr) - write-only this register is used to enable the fifos, clear the fifos, set the transm it/receive fifo trigger levels, and select the dma mode. the dma, and fifo modes are defined as follows: fcr[0]: tx and rx fifo enable ? ? ? ? ? ? ? ?
xr16l2550 26 low voltage duart with 16-byte fifo rev. 1.1.2 fcr[7:6]: receive fifo trigger select (logic 0 = default, rx trigger level =1) these 2 bits are used to se t the trigger level for the receive fifo. th e uart will issue a rece ive interrupt when the number of the characters in the fifo crosses the trigger level. table 10 shows the comple te selections. 4.6 line control register (lcr) - read/write the line control register is used to specify the asynchronous data communication format. the word or character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. lcr[1:0]: tx and rx word length select these two bits specify the word length to be transmitted or received. lcr[2]: tx and rx stop-bit length select the length of stop bit is specified by this bi t in conjunction with the programmed word length. lcr[3]: tx and rx parity select parity or no parity can be selected via this bit. the pa rity bit is a simple way used in communications for data integrity check. see table 11 for parity select ion summary below. ? ?
xr16l2550 27 rev. 1.1.2 low voltage duart with 16-byte fifo lcr[4]: tx and rx parity select if the parity bit is enabled with lcr bit-3 set to a logi c 1, lcr bit-4 selects the even or odd parity format. ? ? ? ? ? ? ? ? ? 4.7 modem control register (mcr) or general purpose outputs control - read/write the mcr register is used for controlling the serial/mod em interface signals or g eneral purpose inputs/outputs. mcr[0]: dtr# output the dtr# pin is a modem control outpu t. if the modem interface is not us ed, this output may be used as a general purpose output. ? ?
xr16l2550 28 low voltage duart with 16-byte fifo rev. 1.1.2 mcr[1]: rts# output the rts# pin is a modem control output. if the modem in terface is not used, this output may be used as a general purpose output. ? ? ? ? ? ? ? ? ? ? ? ? 4.8 line status register (lsr) - read only this register provides the status of data transfers between the uart and the host. lsr[0]: receive data ready indicator ? ?
xr16l2550 29 rev. 1.1.2 low voltage duart with 16-byte fifo lsr[1]: receiver overrun flag ? ? ? ? ? ? ? ? ? ? 4.9 modem status register (msr) - read only this register provides the current state of the modem interface signals, or othe r peripheral device that the uart is connected. lower four bits of this register are used to indicate the changed information. these bits are set to a logic 1 whenever a signal from the modem changes state. these bits may be used as general purpose inputs/outputs when they are not used with modem signals.
xr16l2550 30 low voltage duart with 16-byte fifo rev. 1.1.2 msr[0]: delta cts# input flag ? ? ? ? ? ? ? ? 4.10 scratch pad register (spr) - read/write this is a 8-bit general purpose register for the user to store temporary data. the co ntent of this register is preserved during sleep mode but becomes 0xff (default) after a reset or a power off-on cycle. 4.11 baud rate generator registers (dll and dlm) - read/write the baud rate generator (brg) is a 16-bit counter that generates the data rate for the transmitter. the rate is programmed through registers dll and dlm which are on ly accessible when lcr bit-7 is set to ?1?. see?programmable baud rate genera tor? on page 10. for more details. 4.12 device identification register (dvid) - read only this register contains the device id (0x02 for xr16l25 50). prior to reading this register, dll and dlm should be set to 0x00.
xr16l2550 31 rev. 1.1.2 low voltage duart with 16-byte fifo 4.13 device revision register (drev) - read only this register contains the device revision information. for example, 0x01 means revision a. prior to reading this register, dll and dlm should be set to 0x00. 4.14 enhanced feature register (efr) enhanced features are enabled or disabled using this register. bit 0-3 provide si ngle or dual consecutive character software flow control selection (see table 12 ). when the xon1 and xon2 and xoff1 and xoff2 modes are selected, the double 8-bit words are concatenated in to two sequential characters. caution: note that whenever changing the tx or rx flow control bits, always reset all bits back to logic 0 (disable) before programming a new setting. efr[3:0]: software flow control select single character and dual sequential characters software flow control is supported. combinations of software flow control can be selected by programming these bits. efr[4]: enhanced function bits enable enhanced function control bit. this bit enables ier bits 4-7, isr bits 4-5, and mcr bits 5-7 to be modified. after modifying any enhanced bits, efr bit-4 can be set to a logic 0 to latch the new values. this feature prevents legacy software from altering or overwriting the enhanced functions once set. normally, it is recommended to leave it enabled, logic 1. ? ?
xr16l2550 32 low voltage duart with 16-byte fifo rev. 1.1.2 efr[5]: special character detect enable ? ? ? ? ? ? 4.15 software flow control registers (xoff1, xoff2, xon1, xon2) - read/write these registers are used as the programmable software flow control characters xoff1, xoff2, xon1, and xon2. for more details, see table 6 .
xr16l2550 33 rev. 1.1.2 low voltage duart with 16-byte fifo t able 13: uart reset conditions for channel a and b registers reset state dlm bits 7-0 = 0xxx dll bits 7-0 = 0xxx rhr bits 7-0 = 0xxx thr bits 7-0 = 0xxx ier bits 7-0 = 0x00 fcr bits 7-0 = 0x00 isr bits 7-0 = 0x01 lcr bits 7-0 = 0x00 mcr bits 7-0 = 0x00 lsr bits 7-0 = 0x60 msr bits 3-0 = logic 0 bits 7-4 = logic levels of the inputs inverted spr bits 7-0 = 0xff efr bits 7-0 = 0x00 xon1 bits 7-0 = 0x00 xon2 bits 7-0 = 0x00 xoff1 bits 7-0 = 0x00 xoff2 bits 7-0 = 0x00 i/o signals reset state tx logic 1 op2# logic 1 rts# logic 1 dtr# logic 1 rxrdy# logic 1 txrdy# logic 0 int three-state condition
xr16l2550 34 low voltage duart with 16-byte fifo rev. 1.1.2 test 1: the following inputs must remain steady at vc c or gnd state to minimize sleep current: a0-a2, d0- d7, ior#, iow#, csa#, csb#, and all modem inputs. also, rxa and rxb inputs must idle at logic 1 state while asleep. floating inputs will result in sleep currents in the ma range. for powersave feature that isolates address, data and control signals, please see the xr16l2551 datasheet. absolute maximum ratings power supply range 7 volts voltage at any pin gnd-0.3 v to vcc+0.3 v operating temperature -40 o to +85 o c storage temperature -65 o to +150 o c package dissipation 500 mw typical package thermal resistance data ( margin of error: 15% ) thermal resistance (48-tqfp) theta-ja =59 o c/w, theta-jc = 16 o c/w thermal resistance (44-plcc) theta-ja = 50 o c/w, theta-jc = 21 o c/w thermal resistance (32-qfn) theta-ja = o c/w, theta-jc = o c/w electrical characteristics dc electrical characteristics u nless otherwise noted : ta=-40 o to +85 o c, v cc is 2.25 to 5.5v s ymbol p arameter 2.5v l imits m in m ax 3.3v l imits m in m ax 5.0v l imits m in m ax u nits c onditions v ilck clock input low level -0.3 0.2 -0.3 0.6 -0.5 0.6 v v ihck clock input high level 2.0 5.5 2.4 5.5 3.0 5.5 v v il input low voltage -0.3 0.6 -0.3 0.8 -0.5 0.8 v v ih input high voltage 2.0 5.5 2.0 5.5 2.2 5.5 v v ol output low voltage 0.4 0.4 0.4 v v v i ol = 6 ma i ol = 4 ma i ol = 2 ma v oh output high voltage 1.8 2.0 2.4 v v v i oh = -6 ma i oh = -1 ma i oh = -400 ua i il input low leakage current 10 10 10 ua i ih input high leakage current 10 10 10 ua c in input pin capacitance 5 5 5 pf i cc power supply current 1 1.3 3 ma i sleep sleep current 6 15 30 ua see test 1
xr16l2550 35 rev. 1.1.2 low voltage duart with 16-byte fifo ac electrical characteristics u nless otherwise noted : ta=-40 o to +85 o c, v cc is 2.25v to 5.5v, 70 p f load where applicable s ymbol p arameter l imits 2.5 m in m ax l imits 3.3 m in m ax l imits 5.0 m in m ax u nit - crystal frequency 16 20 24 mhz clk external clock low/high time 31 17 10 ns osc external clock frequency 16 30 50 mhz t as address setup time 10 10 10 ns t ah address hold time 10 10 10 ns t cs chip select width 150 75 50 ns t rd ior# strobe width 150 75 50 ns t dy read cycle delay 150 75 50 ns t rdv data access time 125 70 45 ns t dd data disable time 0 45 0 30 0 30 ns t wr iow# strobe width 150 75 50 ns t dy write cycle delay 150 75 50 ns t ds data setup time 25 20 15 ns t dh data hold time 15 10 10 ns t wdo delay from iow# to output 150 75 50 ns t mod delay to set interrupt from modem input 150 75 50 ns t rsi delay to reset interrupt from ior# 150 75 50 ns t ssi delay from stop to set interrupt 1 1 1 bclk t rri delay from ior# to reset interrupt 150 75 50 ns t si delay from stop to interrupt 150 75 50 ns t int delay from initial int reset to transmit start 8 24 8 24 8 24 bclk t wri delay from iow# to reset interrupt 150 75 50 ns t ssr delay from stop to set rxrdy# 1 1 1 bclk t rr delay from ior# to reset rxrdy# 150 75 50 ns t wt delay from iow# to set txrdy# 150 75 50 ns t srt delay from center of start to reset txrdy# 8 8 8 bclk
xr16l2550 36 low voltage duart with 16-byte fifo rev. 1.1.2 t rst reset pulse width 40 40 40 ns n baud rate divisor 1 2 16 -1 1 2 16 -1 1 2 16 -1 - bclk baud clock 16x of data rate hz f igure 14. c lock t iming f igure 15. m odem i nput /o utput t iming f or c hannels a & b ac electrical characteristics u nless otherwise noted : ta=-40 o to +85 o c, v cc is 2.25v to 5.5v, 70 p f load where applicable s ymbol p arameter l imits 2.5 m in m ax l imits 3.3 m in m ax l imits 5.0 m in m ax u nit osc clk clk external clock iow # rts# dtr# cd# cts# dsr# int ior# ri# t wdo t mod t mod t rsi t mod active active change of state change of state active active active change of state change of state change of state active active
xr16l2550 37 rev. 1.1.2 low voltage duart with 16-byte fifo f igure 16. d ata b us r ead t iming f igure 17. d ata b us w rite t iming t as t dd t ah t rd t rdv t dy t dd t rdv t ah t as t cs valid address valid address valid data valid data a0-a2 csa#/ csb# ior# d0-d7 rdtm t cs t rd 16write t as t dh t ah t wr t ds t dy t dh t ds t ah t as t cs valid address valid address valid data valid data a0-a2 csa#/ csb# iow# d0-d7 t cs t wr
xr16l2550 38 low voltage duart with 16-byte fifo rev. 1.1.2 f igure 18. r eceive r eady & i nterrupt t iming [n on -fifo m ode ] for c hannels a & b f igure 19. t ransmit r eady & i nterrupt t iming [n on -fifo m ode ] for c hannels a & b rx rxrdy# ior# int d0:d7 start bit d0:d7 stop bit d0:d7 t ssr 1 byte in rhr active data ready active data ready active data ready 1 byte in rhr 1 byte in rhr t ssr t ssr rxnfm t rr t rr t rr t ssr t ssr t ssr (reading data out of rhr) tx txrdy# iow# int* d0:d7 start bit d0:d7 stop bit d0:d7 t wt txnonfifo t wt t wt t wri t wri t wri t srt t srt t srt *int is cleared when the isr is read or when data is loaded into the thr. isr is read isr is read isr is read (loading data into thr) (unloading) ier[1] enabled
xr16l2550 39 rev. 1.1.2 low voltage duart with 16-byte fifo f igure 20. r eceive r eady & i nterrupt t iming [fifo m ode , dma d isabled ] for c hannels a & b f igure 21. r eceive r eady & i nterrupt t iming [fifo m ode , dma e nabled ] for c hannels a & b rx rxrdy# ior# int d0:d7 s t ssr rxintdma# rx fifo fills up to rx trigger level or rx data timeout rx fifo drops below rx trigger level fifo empties first byte is received in rx fifo d0:d7 s d0:d7 t d0:d7 s d0:d7 s t d0:d7 s t t d0:d7 s t start bit stop bit t rr t rri t ssi (reading data out of rx fifo) rx rxrdy# ior# int d0:d7 s t ssr rxfifodma rx fifo fills up to rx trigger level or rx data timeout rx fifo drops below rx trigger level fifo empties d0:d7 s d0:d7 t d0:d7 s d0:d7 s t d0:d7 s t t d0:d7 s t start bit stop bit t rr t rri t ssi (reading data out of rx fifo)
xr16l2550 40 low voltage duart with 16-byte fifo rev. 1.1.2 f igure 22. t ransmit r eady & i nterrupt t iming [fifo m ode , dma m ode d isabled ] for c hannels a & b f igure 23. t ransmit r eady & i nterrupt t iming [fifo m ode , dma m ode e nabled ] for c hannels a & b tx txrdy# iow# int* txdma# d0:d7 s d0:d7 t d0:d7 s d0:d7 s t d0:d7 s t t d0:d7 s t start bit stop bit t wri (unloading) (loading data into fifo) last data byte transmitted tx fifo no longer empty data in tx fifo tx fifo empty t wt t srt tx fifo empty t t s t si isr is read ier[1] enabled *int is cleared when the isr is read or when there is at least one character in the fifo. tx txrdy# iow# int* txdma d0:d7 s d0:d7 t d0:d7 s d0:d7 s t d0:d7 s t t d0:d7 s t start bit stop bit t wri (unloading) (loading data into fifo) last data byte transmitted tx fifo no longer empty tx fifo empty tx fifo empty t t s t si isr is read ier[1] enabled *int is cleared when the isr is read or when there is at least one character in the fifo. at least 1 empty location in fifo t srt tx fifo full t wt
xr16l2550 41 rev. 1.1.2 low voltage duart with 16-byte fifo package dimensions (48 pin tqfp - 7 x 7 x 1 mm ) note: the control dimensio n is the millimeter column inches millimeters symbol min max min max a 0.039 0.047 1.00 1.20 a1 0.002 0.006 0.05 0.15 a2 0.037 0.041 0.95 1.05 b 0.007 0.011 0.17 0.27 c 0.004 0.008 0.09 0.20 d 0.346 0.362 8.80 9.20 d1 0.272 0.280 6.90 7.10 e 0.020 bsc 0.50 bsc l 0.018 0.030 0.45 0.75
xr16l2550 42 low voltage duart with 16-byte fifo rev. 1.1.2 package dimensions (44 pin plcc) note: the control dimensio n is the millimeter column inches millimeters symbol min max min max a 0.165 0.180 4.19 4.57 a1 0.090 0.120 2.29 3.05 a2 0.020 --- 0.51 --- b 0.013 0.021 0.33 0.53 b 1 0.026 0.032 0.66 0.81 c 0.008 0.013 0.19 0.32 d 0.685 0.695 17.40 17.65 d1 0.650 0.656 16.51 16.66 d 2 0.590 0.630 14.99 16.00 d 3 0.500 typ. 12.70 typ. e 0.050 bsc 1.27 bsc h 1 0.042 0.056 1.07 1.42 h 2 0.042 0.048 1.07 1.22 r 0.025 0.045 0.64 1.14 44 lead plastic leaded chip carrier (plcc) rev. 1.00 1 d d 1 a a 1 d d 1 d 3 b a 2 b 1 e seating plane d 2 244 d 3 c r 45
xr16l2550 43 rev. 1.1.2 low voltage duart with 16-byte fifo package dimensions (32 pin qfn - 5 x 5 x 0.9 mm ) note: the control dimension is in millimeter. inches millimeters symbol min max min max a 0.031 0.039 0.80 1.00 a1 0.000 0.002 0.00 0.05 a3 0.006 0.010 0.15 0.25 d 0.193 0.201 4.90 5.10 d2 0.138 0.150 3.50 3.80 b 0.007 0.012 0.18 0.30 e 0.0197 bsc 0.50 bsc l 0.012 0.020 0.35 0.45 k 0.008 - 0.20 - note: the actual center pad is metallic and the size (d2) is device-dependent with a typical tolerance of 0.3mm
44 notice exar corporation reserves the right to make changes to the products contained in this publicat ion in order to improve design, performanc e or reliability. exar corp oration assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infr ingement. charts and schedules contai ned here in are only for illustration purposes and may vary depending upon a user?s specific application. while the information in this publication has been carefully ch ecked; no responsibility, however , is assumed for inaccuracies. exar corporation does not re commend the use of any of its products in life suppo rt applications where the failure or malfunction of the product can reasonably be ex pected to cause failure of the life support system or to significantly affect its safety or effectiveness. products ar e not authorized for use in such applications unless exar corporation receives , in writing, assuranc es to its satisfaction that: (a) th e risk of injury or damage has been minimized; (b) th e user assumes all such ris ks; (c) potential liability of exar corporation is adequately protected under the circumstances. copyright 2007 exar corporation datasheet may 2007. send your uart technical inquiry with technical details to hotline: uarttechsupport@exar.com . reproduction, in part or whole, without the prior written consent of exar co rporation is prohibited. xr16l2550 low voltage duart with 16-byte fifo rev. 1.1.2 revision history d ate r evision d escription november 2002 p1.0.0 preliminary datasheet. march 2003 p1.0.1 updated ac electrical characteristics. u pdated register set with enhanced features. may 2003 p1.0.2 added patent number to first page. added 32 pin qfn package dimensions. june 2003 p1.0.3 added device status to ordering information. july 2003 p1.0.4 updated ac electrical characteristics. september 2003 1.0.0 final production release. updated 5v tolerance information. september 2004 1.1.0 corrected 32-qfn package dimension descr iptions. added gnd center pad pin description. added device revision and device id registers and descriptions. may 2005 1.1.1 updated the data access time (t rdv ) in ac electrical characteristics. may 2007 1.1.2 updated qfn package dimensions drawing to show minimum "k" parameter.
xr xr16l2550 low voltage duart with 16-byte fifo rev. 1.1.2 i table of contents general description........ ................. ................ ................ ............... .............. ........... 1 a pplications ............................................................................................................................... ................ 1 f eatures ............................................................................................................................... ...................... 1 f igure 1. xr16l2550 b lock d iagram ............................................................................................................................... .......... 1 f igure 2. p in o ut a ssignment ............................................................................................................................... ...................... 2 ordering information ............................................................................................................................... .2 pin descriptions ............ ................ ................ ................. ................ ................. ........... 3 1.0 product description ..................................................................................................... ............... 6 2.0 functional descriptions ................................................................................................. ........... 7 2.1 cpu interface ........................................................................................................... .................................. 7 f igure 3. xr16l2550 d ata b us i nterconnections .................................................................................................................. 7 2.2 5-volt tolerant inputs .... .............. .............. .............. .............. .............. .............. .......... ......................... 7 2.3 device reset ..... .............. .............. .............. .............. .............. ........... ........... ........... .................................... 7 2.4 device identification and revision ........... ........................................................................... .............. 7 2.5 channel a and b selection .... .............. .............. .............. .............. .............. ........... .......... .................... 7 t able 1: c hannel a and b s elect ............................................................................................................................... ................ 8 2.6 channel a and b internal registers ................ .............. .............. .............. .............. .............. .......... 8 2.7 dma mode ................................................................................................................ ...................................... 8 t able 2: txrdy# and rxrdy# o utputs in fifo and dma m ode ............................................................................................. 8 2.8 inta and intb outputs ................................................................................................... ........................... 8 t able 3: inta and intb p ins o peration for t ransmitter ........................................................................................................ 9 t able 4: inta and intb p in o peration f or r eceiver ............................................................................................................... 9 2.9 crystal oscillator or external clock input ..... .............. .............. .............. ............ ........... ....... 9 f igure 4. t ypical oscillator connections ............................................................................................................................... .. 9 2.10 programmable baud rate generat or .............. .............. .............. ........... ........... ........... ............ .. 10 f igure 5. e xternal c lock c onnection for e xtended d ata r ate .......................................................................................... 10 f igure 6. o perating f requency c hart . r equires a 2k ohms pull - up resistor on xtal2 pin to increase operating speed 10 t able 5: t ypical data rates with a 14.7456 mh z crystal or external clock ...................................................................... 11 2.11 transmitter ....... .............. .............. .............. .............. ........... ........... ........... ............ ................................. 11 2.11.1 transmit holding register (thr) - write only.......................................................................... ............. 11 2.11.2 transmitter operatio n in non-fifo mode ................................................................................ ................ 11 f igure 7. t ransmitter o peration in non -fifo m ode .............................................................................................................. 12 2.11.3 transmitter operation in fifo mode .................................................................................... ..................... 12 f igure 8. t ransmitter o peration in fifo and f low c ontrol m ode ..................................................................................... 12 2.12 receiver ............................................................................................................... ..................................... 12 2.12.1 receive holding register (rhr) - read-only ............................................................................ .............. 13 f igure 9. r eceiver o peration in non -fifo m ode .................................................................................................................... 13 f igure 10. r eceiver o peration in fifo and a uto rts f low c ontrol m ode ....................................................................... 13 2.13 auto rts (hardware) flow co ntrol ............... .............. .............. ........... ........... ............ .......... ...... 14 2.14 auto cts flow control ................................................................................................. .................... 14 f igure 11. a uto rts and cts f low c ontrol o peration ....................................................................................................... 15 2.15 auto xon/xoff (software) flow control .................................................................................. . 16 t able 6: a uto x on /x off (s oftware ) f low c ontrol ............................................................................................................... 16 2.16 special character detect .. .............. .............. .............. .............. .............. ........... ........... ................. 16 2.17 infrared mode ..... .............. .............. .............. .............. .............. ........... ........... ......... .............................. 17 f igure 12. i nfrared t ransmit d ata e ncoding and r eceive d ata d ecoding .......................................................................... 17 2.18 sleep mode with auto wake-u p ............. .............. .............. .............. .............. ........... .......... ............ 18 2.19 internal loopback ..................................................................................................... ......................... 19 f igure 13. i nternal l oop b ack in c hannel a and b ................................................................................................................ 19 3.0 uart internal registers ................................................................................................. .......... 20 t able 7: uart channel a and b uart internal registers ............................................................................ ......... 20 t able 8: internal registers description. s haded bits are enabled when efr b it -4=1......................................... 21 4.0 internal register descriptions .......................................................................................... .. 22 4.1 receive holding register (rhr) - read- only . .............. .............. .............. ........... ........... ............ .. 22 4.2 transmit holding register (thr) - write-only ............................................................................ 22 4.3 interrupt enable register (ier ) - read/write .......... .............. .............. .............. .............. .......... . 22 4.3.1 ier versus receive fifo interrupt mode operation ....................................................................... ...... 22 4.3.2 ier versus receive/transmit fifo polled mode operation................................................................ 22 4.4 interrupt status register (isr) - read-only ............................................................................. .. 23
xr16l2550 xr rev. 1.1.2 low voltage duart with 16-byte fifo ii 4.4.1 interrupt generation: .................................................................................................. .................................... 24 4.4.2 interrupt clearing: .................................................................................................... ....................................... 24 t able 9: i nterrupt s ource and p riority l evel ....................................................................................................................... 24 4.5 fifo control register (fcr) - write-only ................................................................................ ...... 25 t able 10: r eceive fifo t rigger l evel s election ................................................................................................................... 26 4.6 line control register (lcr) - read/write ................................................................................ ...... 26 t able 11: p arity selection ............................................................................................................................... ......................... 27 4.7 modem control register (mcr) or gene ral purpose outputs control - read/write 27 4.8 line status register (lsr) - read only .................................................................................. ......... 28 4.9 modem status register (msr) - read only ................................................................................. ... 29 4.10 scratch pad register (spr) - read/write ................................................................................ .... 30 4.11 baud rate generator registers (dll and dlm) - read/write ...... ........... ........... ........... ....... 30 4.12 device identification register (dvid) - read only .................................................................... 3 0 4.13 device revision register (drev) - read only ............................................................................ .. 31 4.14 enhanced feature register (efr) ........................................................................................ .......... 31 t able 12: s oftware f low c ontrol f unctions ........................................................................................................................ 31 4.15 software flow control registers (xoff1, xoff2, xon1, xon2) - read/write ................ 32 t able 13: uart reset conditions for channel a and b................................................................................ ............ 33 absolute maximum ratings........... ................ ................ ............... .............. ...........34 typical package thermal resistance data (margin of error: 15%) 34 electrical characteristics ........ ................ ................ ............... .............. ...........34 dc e lectrical c haracteristics ..............................................................................................................34 ac e lectrical c haracteristics ..............................................................................................................35 unless otherwise noted: ta=-40o to +85oc, vcc is 2.25v to 5.5v, ................................................................ .......... 35 70 pf load where applicable.................................................................................................... .................................. 35 f igure 14. c lock t iming ............................................................................................................................... .............................. 36 f igure 15. m odem i nput /o utput t iming f or c hannels a & b ................................................................................................. 36 f igure 17. d ata b us w rite t iming ............................................................................................................................... .............. 37 f igure 16. d ata b us r ead t iming ............................................................................................................................... ............... 37 f igure 18. r eceive r eady & i nterrupt t iming [n on -fifo m ode ] for c hannels a & b ......................................................... 38 f igure 19. t ransmit r eady & i nterrupt t iming [n on -fifo m ode ] for c hannels a & b ....................................................... 38 f igure 20. r eceive r eady & i nterrupt t iming [fifo m ode , dma d isabled ] for c hannels a & b........................................ 39 f igure 21. r eceive r eady & i nterrupt t iming [fifo m ode , dma e nabled ] for c hannels a & b......................................... 39 f igure 22. t ransmit r eady & i nterrupt t iming [fifo m ode , dma m ode d isabled ] for c hannels a & b............................ 40 f igure 23. t ransmit r eady & i nterrupt t iming [fifo m ode , dma m ode e nabled ] for c hannels a & b ............................ 40 package dimensions (48 pin tqfp - 7 x 7 x 1 mm)... ................ ................. ...........41 package dimensions (44 pin plcc ) ................. .............. ............... .............. ...........42 package dimensions (32 pin qfn - 5 x 5 x 0.9 mm)... ............... ................. ...........43 r evision h istory ............................................................................................................................... ........44 t able of c ontents ................ ................. ................ ................ ............... .............. .............. i

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